The present invention relates to the field of electronic circuits, and, more particularly, to a digital clock generator circuit with built-in frequency and duty cycle control.
More and more circuitry is being included in application specific integrated circuit (ASIC) chips. The technology trends are following Moore""s law. As a result, every year the technology shrinks roughly by a factor of 1.5. For example, high speed clock generation, which formerly was done externally (e.g., using automatic test equipment), is now being done on-board the chip itself.
The variable duty cycle generator can be produced by performing Boolean operations on the clock and by phase delay of the clock. Phase delay is obtained by using a chain of delay logic elements. Outputs are taken at various points along the chain to get clocks with different phase. If both phase change and variable frequency are required, then two different circuits will be needed. If the duty cycle variation is done through a separate circuit, the resolution of the duty cycle can be maintained at sufficient levels, but the range of the duty cycle will be low. Further, a good ratio of the duty cycle resolution to the clock frequency cannot be maintained with decreasing frequency.
An object of the invention is to provide a digital clock generator circuit with built-in frequency and duty cycle control which provides a good range of duty cycle for the full frequency range.
Another object of the invention is to provide a digital clock generator circuit with built-in frequency and duty cycle control, independent of the technology process used for manufacture, as well as special patterns for frequency generation.
Yet another object of the invention is to provide a circuit which provides a variable duty cycle at various frequencies where the variation is automatically proportionate to the frequency of the clock.
To achieve the above objectives, the invention provides a digital clock generator circuit with built-in frequency and duty cycle control which may include a pulse generator block for generating a start pulse. The pulse generator may be connected to a ring oscillator block to generate multiple signals having a specified frequency and programmable duty cycles. Further, the ring oscillator block may be connected to a multiplexer block which selectively connects one of the outputs of the ring oscillator to the final output to produce a signal of the specified frequency and specified duty cycle. As a result, the duty cycle may be adjustable over a wide range and across the full frequency band of operation.
The pulse width of the start pulse may be controlled through a pulse width controller built into the pulse generator. Further, the ring oscillator block may include flip-flops connected in cascade, with the output of one flip-flop connected to the clock input of the next flip-flop and the output of the last flip-flop connected to the clock input of the first flip-flop to form a ring. The flip-flops may be arranged in two halves, each having an equal number of flip-flops, where the clear input of the flip-flops of each half are connected to a global reset. Additionally, a programmable delay means or circuit may be provided in the global reset path to avoid recovery and hold time problems. Also, a multiplexer block may be included to selectively change the number of flip-flops connected in cascade to vary the frequency generated.
The number of flip-flops in each of the halves may depend upon the frequency of generation and duty cycle. The duration of the pulse output from the pulse generator may be programmable between four different values based on the logic levels of the input signals PW_STROBE0 and PW_STROBE1, for example. The data input of each of the flip-flops of both the halves may be connected to logic 1 if the global reset is connected to its clear input, and to a logic 0 if the global reset is connected to its preset input.
The multiplexer block may select one of the outputs from the ring oscillator to provide a signal of the required duty cycle. The resolution of the high time adjustment may be defined as Td=1/NF, and the duty cycle variation may be defined as Tdc=1/N, where N is the number of flip-flops in the ring of flip-flops and F is the frequency at any point of the chain. Also, the digital clock generator circuit may be used to measure the propagation delay of the flip-flop elements included therein.